Cypress Semiconductor /psoc63 /CTBM0 /OA_RES1_CTRL

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Interpret as OA_RES1_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0OA1_PWR_MODE 0 (OA1_DRIVE_STR_SEL)OA1_DRIVE_STR_SEL 0 (OA1_COMP_EN)OA1_COMP_EN 0 (OA1_HYST_EN)OA1_HYST_EN 0 (OA1_BYPASS_DSI_SYNC)OA1_BYPASS_DSI_SYNC 0 (OA1_DSI_LEVEL)OA1_DSI_LEVEL 0 (DISABLE)OA1_COMPINT 0 (OA1_PUMP_EN)OA1_PUMP_EN 0 (OA1_BOOST_EN)OA1_BOOST_EN

OA1_COMPINT=DISABLE

Description

Opamp1 and resistor1 control

Fields

OA1_PWR_MODE

Opamp1 power level: see description of OA0_PWR_MODE

OA1_DRIVE_STR_SEL

Opamp1 output strength select 0=1x, 1=10x This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM

OA1_COMP_EN

Opamp1 comparator enable

OA1_HYST_EN

Opamp1 hysteresis enable (10mV)

OA1_BYPASS_DSI_SYNC

Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass

OA1_DSI_LEVEL

Opamp1 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output

OA1_COMPINT

Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)

0 (DISABLE): Disabled, no interrupts will be detected

1 (RISING): Rising edge

2 (FALLING): Falling edge

3 (BOTH): Both rising and falling edges

OA1_PUMP_EN

Opamp1 pump enable

OA1_BOOST_EN

Opamp1 gain booster enable for class A output, for risk mitigation only, not user selectable. Value depends on the drive strength setting - 1x mode: set to 1; 10x mode: set to 0

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